It has been developed with Rescale.SAFE CDP supports a design condition that has been verified with cloud companies. In addition, customers can utilise various EDA tools offered by multiple vendors such as Ansys, Cadence, Mentor, a Siemens business and Synopsys.Gaonchips, one of Samsung Foundry’s Design Solution Partners, has already tested the SAFE CDP on its 14nm automotive project using Cadence’s Innovus Implementation System and has successfully reduced its design run-time by 30 percent compared to current on-premise executionAs designs move to advanced nodes and as transistor scaling occurs at each node, chip designs become more complex and computing power required for these designs have increased significantly, resulting in greater overhead time and cost to customers.By adopting CDP, customers can reduce the burden of building their own server infrastructure, while flexibly utilizing additional computing power required for chip design and verification. Furthermore, they can take full advantage of Samsung’s diverse foundry ecosystem which includes EDA, intellectual property (IP), cloud, and design services offered by reputable partners.
“We are excited to be a partner of Samsung Foundry SAFE™ ecosystem,” said Joris Poort, founder and CEO of Rescale. “We share a common vision of a global design cloud platform that efficiently supports a broad ecosystem of technologies and services for EDA customers worldwide.To actively respond to the latest technology trends and lower the design barrier for developing competitive SoCs, Samsung launched the SAFE™ program in early 2018 and held the first SAFE™ Forum in the United States last year.
Source : This news is taken from www.electronicsweekly.com
